Many electrical and computer applications and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop ("PLL") is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a reference or input signal. Wireless communication devices, frequency synthesizers, multipliers and dividers, single and multiple clock generators, and clock recovery circuits are but a few examples of the manifold implementations of PLLs.
Frequency synthesis is a particularly common technique used to generate a high frequency clock from a lower frequency reference clock. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency input (off-chip) clock, typically in the range of 1 to 4 MHz, to generate a high frequency output clock, typically in the range of 10 to over 200 MHz, that is precisely synchronized with the lower frequency external clock. Another common use of PLLs is recovery of digital data from serial data streams by locking a local clock signal onto the phase and frequency of the data transitions. The local clock signal is then used to clock a flip-flop or latch receiving input from the serial data stream.
FIG. 1 is a block diagram of a typical PLL 10. PLL 10 comprises phase/frequency detector 12, charge pump 14, loop filter 16, voltage-controlled oscillator ("VCO") 18 and frequency divider 20. PLL 10 receives a reference clock signal CLK.sub.REF having a frequency F.sub.REF and generates an output clock signal CLK.sub.OUT having a frequency F.sub.OUT that is aligned to the reference clock signal in phase. The output clock frequency is typically an integer (N) multiple of the reference clock frequency; with the parameter N set by frequency divider 20. Hence, for each reference signal period, there are N output signal periods or cycles.
Phase/frequency signal detector 12 receives on its input terminals two clock signals CLK.sub.REF and CLK*.sub.OUT (CLK.sub.OUT, with its frequency F.sub.OUT divided down by frequency divider 20). In a conventional arrangement, detector 12 is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, detector 12 generates one of three states. If the phases of the two signals are aligned, the loop is "locked". Neither the UP nor the DOWN signal is asserted and VCO 18 continues to oscillate at the same frequency. If CLK.sub.REF leads CLK*.sub.OUT, than VCO 18 is oscillating too slowly and detector 12 outputs an UP signal proportional to the phase difference between CLK.sub.REF and CLK*.sub.OUT. Conversely, if CLK.sub.REF lags CLK*.sub.OUT, than VCO 18 is oscillating too quickly and detector 12 outputs a DOWN signal proportional to the phase difference between CLK.sub.REF and CLK*.sub.OUT. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals.
Charge pump 14 generates a current I.sub.CP that controls the oscillation frequency F.sub.OUT of VCO 18. I.sub.CP is dependent on the signal output by phase/frequency detector 12. If charge pump 14 receives an UP signal from detector 12, indicating that CLK.sub.REF leads CLK*.sub.OUT, I.sub.CP is increased. If charge pump 14 receives a DOWN signal from detector 12, indicating that CLK.sub.REF lags CLK*.sub.OUT, I.sub.CP is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals are aligned, charge pump 14 does not adjust I.sub.CP.
Loop filter 16 is positioned between charge pump 14 and VCO 18. Application of the charge pump output current I.sub.CP to loop filter 16 develops a voltage V.sub.LF across filter 16. V.sub.LF is applied to VCO 18 to control the frequency F.sub.OUT of the output clock signal. Filter 16 also removes out-of-band, interfering signals before application of V.sub.LF to VCO 18. A common configuration for a loop filter in a PLL is a simple single-pole, low-pass filter that can be realized with a single resistor and capacitor.
Oscillator 18 generates an oscillating output signal CLK.sub.OUT having a frequency F.sub.OUT proportional to the voltage V.sub.LF applied to VCO 18. Conventional voltage-controlled oscillators typically oscillate about a specific center frequency and have a relatively narrow frequency range or bandwidth. When CLK.sub.REF leads CLK*.sub.OUT, charge pump 14 increases I.sub.CP to develop a greater V.sub.LF across loop filter 16 which, in turn, causes VCO 18 to increase F.sub.OUT. Conversely, when CLK.sub.REF lags CLK*.sub.OUT, charge pump 14 decreases I.sub.CP to develop a lesser V.sub.LF across loop filter 16 which, in turn, causes VCO 18 to decrease F.sub.OUT. When CLK.sub.REF and CLK*.sub.OUT are aligned, V.sub.LF is not adjusted, and F.sub.OUT is kept constant. In this state, PLL 10 is in a "locked" condition.
The output clock signal is also looped back through (in some applications) frequency divider 20. The resultant output CLK*.sub.OUT is provided to phase/frequency detector 12 to facilitate the phase-locked loop operation. Frequency divider 20 facilitates comparison of the generally higher frequency output clock signal with the lower frequency reference clock signal by dividing F.sub.OUT by the multiplication factor N. Divider 20 may be implemented using counters, shift registers, or through other methods familiar to those of ordinary skill in the art. Thus, PLL 10 compares the reference clock phase to the output clock phase and eliminates any detected phase difference between the two by adjusting the frequency of the output clock.
As described above, phase-locked loops conventionally employ voltage-controlled oscillators to generate the output clock signal. Voltage-controlled oscillators, in turn, are often implemented in the form of ring oscillators. Ring oscillators are well known in the art and are typically comprised of an odd number of inverters connected in cascade, with the output of the last inverter in the series being connected to the input of the first inverter. Hence, the oscillator alternately generates logical ones and zeroes that propagate around the ring. Each inverter also acts as a delay element, wherein the delay of the inverter contributes to the oscillation period.
Ring oscillators are plagued by several drawbacks. Of chief concern, relative to the present invention, is the tendency of ring oscillators to accumulate a significant amount of jitter. Jitter is phase noise that is generated during PLL operation from a number of sources, including switching activity and substrate and supply noise. Each inverter generates a quantum of jitter that is transferred to successive stages. As the ring oscillator is essentially a continuous feedback loop, the jitter continuously propagates and accumulates. The jitter-per-cycle of a PLL employing a ring oscillator is expressed by the sum of the timing error contributed by each inverter weighted by the correction provided by the loop. The z-domain transfer function, .THETA..sub.out (z), for the phase error of a PLL employing a ring oscillator may be represented as: ##EQU1##
where K.sub.d is the gain of the phase detector, K.sub.VCO is the gain of the VCO, and Z.sub.F (z) is the z-domain transfer function of the loop filter. Assuming a first order loop filter transfer function is used, the z-domain transfer function for phase error becomes: ##EQU2##
where .epsilon.=K.sub.d K.sub.VCO aT and is smaller than one, wherein a is the DC gain of loop filter 16 and T is the period of the input reference signal ##EQU3##
and .THETA..sub.n (z) is the z-transform of the phase of the input reference signal.
The phase jitter of a ring oscillator can be modeled as a sequence of unit step phase jumps with random magnitude. A single-phase jump at time nT can be expressed in the z-domain as: ##EQU4##
Hence, the resulting phase error in the z-domain is: ##EQU5##
The square of the phase error can be written as: ##EQU6##
The r.m.s. of the phase error, which is a measure of the phase jitter in the output of the VCO due to noise is: ##EQU7##
where the accumulation factor, .alpha., is ##EQU8##
The PLL bandwidth can be expressed as EQU .omega..sub.L.apprxeq.K.sub.VCO K.sub.d a, so: ##EQU9##
where .omega..sub.REF is the reference or comparison frequency F.sub.REF of the phase detector.
FIG. 7, which plots the accumulation factor .alpha. vs. the loop bandwidth/reference frequency ratio .epsilon., demonstrates the jitter accumulation demonstrated by a PLL employing a ring oscillator over a range of bandwidths. The figure demonstrates that reducing loop bandwidth can reduce the accumulation factor. The problem is that there are limits to the extent to which loop bandwidth can be reduced and still maintain loop stability. In one implementation example, loop stability is maintained if the loop bandwidth is above about 100% of the reference frequency. Therefore, decreasing PLL bandwidth is at best a limited option for reducing jitter.
In view of the above, there is a need for a clock generation circuit that overcomes the disadvantages of the prior art.